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PRELIMINARY
CY22180
Very Low Jitter Field and Factory Programmable Clock Generator
Features
* Low period and cycle-to-cycle jitter -- Typical pk-pk period jitter: 60 ps * Wide output frequency range -- Commercial temperature: 20-200 MHz -- Industrial temperature: 20-166 MHz * Input frequency range -- External crystal: 10-30 MHz fundamental crystal * * * * * * -- External reference: 10-133 MHz clock Integrated phase-locked loop (PLL) Field programmable and factory programmed options Programmable crystal load capacitor tuning array 3.3V operation Commercial and industrial temperature ranges Power down or output enable function
Benefits
* Internal PLL generates up to 200 MHz output. Can generate custom frequencies from an external crystal or a driven source. * In-house programming of samples and prototype quantities can be done using the CY3672-USB programmer and CY3619 socket adapter. Production quantities are available through Cypress's value added distribution partners or by using third party programmers from BP Microsystems, HiLo Systems, and others. * Eliminates the need for expensive and difficult to use higher-order crystals. * Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. * Application compatibility in standard and low-power systems * Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
Pin Configuration
CY22180 8-pin SOIC
1 XIN/CLKIN CXIN 8 XOUT CXOUT
PLL
OUTPUT DIVIDER
6 CLKOUT
1 XIN/CLKIN
PROGRAMMABLE CONFIGURATION 5 REFOUT
XOUT 8
2 VDD
NC 7
3 PD#/OE
CLKOUT 6
3 PD# or OE 2 VDD 4 VSS
4 VSS
REFOUT 5
Cypress Semiconductor Corporation Document #: 001-15577 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised May 10, 2007
PRELIMINARY
CY22180
Pin Description
Pin 1 2 3 VDD PD#/OE Name XIN/CLKIN 3.3V power supply. Power down pin, active LOW. If PD# = 0, the PLL and oscillator are powered down and outputs are weakly pulled low. Output enable pin, active HIGH. If OE = 1, CLKOUT and REFOUT are enabled. User has the option of choosing either PD# or OE function. 4 5 6 7 8 VSS REFOUT CLKOUT NC XOUT Power supply ground. Buffered reference output. Low jitter clock output. No connect. Leave this pin floating. Crystal output. Leave this pin floating if external clock is used. programmed into the CY22180. CyberClocks Online outputs an industry-standard JEDEC file used for programming the CY22180. CyberClocks Online is available at www.cyberclocksonline.com through user registration. For more information on the registration process refer to the CY3672 data sheet. CY3672-USB Programming Kit and CY3619 Socket Adapter The Cypress CY3672 FTG programmer and CY3619 socket adapter are needed to program the CY22180. The socket adapter comes with small prototype quantities of CY22180. The CY3619 can be ordered separately, so existing users of the CY3672-USB programmer need order only the socket adapters to program the CY22180. Factory Programmed CY22180 Factory programming is available for volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number (dash number) and samples with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY22180 can be obtained from the Cypress website at www.cypress.com. Description Crystal input or reference clock input.
General Description
The CY22180 is a low jitter clock generator for use in networking, telecommunication, datacom, consumer electronics, and other general purpose applications. The CY22180 offers a single programmable output and an optional copy of the input frequency. The on-chip reference oscillator is designed to run off a 10-30 MHz crystal, or a 10-133 MHz external clock signal. The output frequency range is 20-200 MHz. The CY22180 comes in an 8-pin SOIC, and requires a 3.3V power supply.
Programming Description
Field Programmable (CY22180FSXC and CY22180FSXI) The CY22180 is programmed at the package level, that is, in a programmer socket. The CY22180 is flash technology based, so the parts can be reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities can be programmed on the CY3672 programmer with the CY3619 socket adapter. CyberClocksTM Online Software CyberClocks Online Software is a web-based software application that allows the user to custom-configure the CY22180. All the parameters in Table 1 given as "Enter Data" can be Table 1. Pin Function Pin Name Pin# Unit Program Value Input Frequency XIN and XOUT 1 and 8 MHz ENTER DATA Total Xtal Load Capacitance XIN and XOUT 1 and 8 pF ENTER DATA
Output Frequency CLKOUT 6 MHz ENTER DATA
Reference Output REFOUT 5 On or Off ENTER DATA
Power-down or Output Enable PD#/OE 3 Select PD# or OE ENTER DATA
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PRELIMINARY
Product Functions
Input Frequency (XIN, pin 1 and XOUT, pin 8) The input to the CY22180 can be a crystal or a clock. The input frequency range for crystals is 10 to 30 MHz, and for clock signals is 10 to 133 MHz. CXIN and CXOUT (pin 1 and pin 8) The internal load capacitors at pin 1 (CXIN) and pin 8 (CXOUT) can be programmed from 12 pF to 60 pF in 0.5-pF increments. Thus, these programmable capacitors support crystals with CL values between 6 pF and 30 pF. The crystal CL value, minus board parasitic capacitance, is the value entered into CyberClocks Online Software. If using a driven reference, CyberClocks Online Software will set CXIN and CXOUT to the minimum value 12 pF. Output Clock (CLKOUT, pin 6)
CY22180
The output clock can be programmed to any frequency in the range of 20-200 MHz. Reference Output (REFOUT, pin 5) The reference clock output has the same frequency as the input clock. This output can be programmed to be enabled (clock on) or disabled (High-Z, clock off) through CyberClocks Online software. If this output is not needed, Cypress recommends that users request the disabled (High-Z, Clock Off) option. Power Down or Output Enable (PD# or OE, pin 3) The CY22180 can be programmed to include either PD# or OE function. PD# function can be used to power down the oscillator and PLL. The OE function disables the outputs but does not turn off the PLL. PD# achieves lower power consumption, but PLL start up time means that turn-on time is slower than for OE.
Absolute Maximum Ratings
Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-condensing)..... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015)
Recommended Crystal Specifications
Parameter FNOM CLNOM R1 DL Description Nominal Crystal Frequency Nominal Load Capacitance Equivalent Series Resistance (ESR) Fundamental mode Crystal Drive Level No external series resistor assumed Comments Parallel resonance, fundamental mode, AT cut Min. 10 6 - - Typ. - - - 0.5 Max. 30 30 25 2 Unit MHz pF mW
Operating Conditions
Parameter VDD TA CLOAD FXIN FCLKIN FCLKOUT FREFOUT TPU Supply Voltage Ambient Commercial Temperature Ambient Industrial Temperature Max. Load Capacitance @ pin 5 and pin 6 External Reference Crystal External Reference Clock CLKOUT frequency, Commercial Temperature CLKOUT frequency, Industrial Temperature REFOUT frequency Power-up time for all VDDs to reach minimum specified voltage (power ramp must be monotonic) Description Min. 3.13 0 -40 - 10 10 20 20 10 0.05 Typ. 3.30 - - - - - - - - - Max. 3.45 70 85 10 30 133 200 166 133 500 Unit V C C pF MHz MHz MHz MHz MHz ms
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PRELIMINARY
l
CY22180
DC Electrical Characteristics
Parameter
IOH IOL VIH VIL IIH IIL IOZ CXIN or CXOUT CIN[1] IDD IDDS
[1]
Description
Output High Current Output Low Current Input High Voltage Input Low Voltage
Condition
VOH = VDD - 0.5V, VDD = 3.3V (source) VOL = 0.5V, VDD = 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD
Min
10 10 0.7VDD -0.3 - - - -10 - - -
Typ
12 12 - - - - - 12 60 5 11 10
Max
Unit
mA mA
VDD + 0.3 0.3VDD 10 10 55 10 - - 7 15 40
V V A A A A pF pF pF mA A
Input High Current, PD#/OE VIN= VDD Input Low Current, PD#/OE VIN = VSS, pull up disabled VIN = VSS, pull up enabled Output Leakage Current Three-state output, PD#/OE = 0 Programmable Capacitance Capacitance at minimum setting at pin 1 and pin 8 Capacitance at maximum setting Input Capacitance at PD#/OE Supply Current Standby current fIN = 10 MHz, fOUT = 33 MHz, REFOUT off Device powered down with PD# = 0V (driven reference pulled down)
- -
AC Electrical Characteristics[1]
Parameter DC Description Output Duty Cycle Output Duty Cycle Output Duty Cycle SR1 SR2 TPJ1[2, 3] TPJ2[2, 3] Rising Edge Slew Rate Falling Edge Slew Rate CLKOUT pk-pk Period Jitter, REFOUT off Condition CLKOUT < 125 MHz, Measured at VDD/2 CLKOUT > 125 MHz, Measured at VDD/2 REFOUT, Measured at VDD/2 Duty Cycle of CLKIN = 50% CLKOUT from 20 to 200 MHz; REFOUT from 10 to 133 MHz. 20%-80% of VDD CLKOUT from 20 to 200 MHz; REFOUT from 10 to 133 MHz. 80%-20% of VDD CLKOUT = 20-200 MHz Min 45 40 45 2 2 - - - - - - - - Typ 50 50 50 3 3 - - - - - - - - Max 55 60 55 - - 75 (38) 60 (30) 56 (28) 62 (31) 47 (24) 68 (34) 68 (34) 52 (26) Unit % % % V/ns V/ns ps ps ps ps ps ps ps ps
CLKIN = 10 MHz, CLKOUT = 20, 33, 66, 80, CLKOUT pk-pk Period Jitter, REFOUT off, specific 106.25, 125, 133, or 200 MHz frequencies CLKIN = 25 MHz, CLKOUT = 125 MHz CLKIN = 30 MHz, CLKOUT = 33, 66, 80, 106.25, 125, or 133 MHz CLKIN = 66 MHz, CLKOUT = 33 or 66 MHz CLKIN = 66 MHz, CLKOUT = 80, 106.25, 125, 133, 166, or 200 MHz CLKIN = 133 MHz, CLKOUT = 33, 66, or 80 MHz CLKIN = 133 MHz, CLKOUT = 125, 133, or 166 MHz
Notes 1. Guaranteed by characterization, not 100% tested. 2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, temperature, and output load. For more information, refer to the application note, "Jitter in PLL Based Systems: Causes, Effects, and Solutions". 3. Cycle-to-Cycle Jitter (peak) is always less than Period Jitter (peak-to-peak). Peak-to-Peak Period Jitter is the difference between the shortest and longest measured periods.
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PRELIMINARY
AC Electrical Characteristics[1]
Parameter TPJ3[2, 3] TPJ4[2, 3] tSTP TOE1 TOE2 tPU1 tPU2 Description CLKOUT pk-pk Period Jitter, REFOUT on Condition CLKOUT = 20-200 MHz Min - - - - - - - Typ 150 (75) - 150 150 150 3.5 2
CY22180
Max - 265 (133) 350 350 350 5 3
Unit ps ps ns ns ns ms ms
REFOUT pk-pk Period Jitter REFOUT = 10-133 MHz Power Down Time (pin 3 = PD#) Output Disable Time (pin 3 = OE) Output Enable Time (pin 3 = OE) Power Up Time, Crystal is used Power Up Time, Reference clock is used Time from falling edge on PD# to stopped outputs (Asynchronous) Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous), reference clock at correct frequency
Application Circuits[4, 5]
Crystal
Power
1 XIN/CLKIN
XOUT 8
CLKIN Power
1 XIN/CLKIN
XOUT 8
no connect no connect
2
VDD
NC 7
no connect
0.1uF VDD or control
2
VDD
NC 7
0.1uF VDD or control
CY22180
3 PD#/OE
CY22180
3 PD#/OE
CLKOUT 6
CLKOUT 6
4 VSS
REFOUT 5
4 VSS
REFOUT 5
Notes 4. Since the load capacitors (CXIN and CXOUT) are provided by the CY22180, no external capacitors are needed on the XIN and XOUT pins to match the crystal load capacitor (CL). Only a single 0.1-F bypass capacitor is required on the VDD pin. 5. If an external clock is used, apply the clock to XIN (pin 1) and leave XOUT (pin 8) floating (unconnected).
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PRELIMINARY
CY22180
Switching Waveforms
Figure 1. Duty Cycle Timing (DC = t1A/t1B)
t1A t1B
OUTPUT
Figure 2. Output Rise/Fall Time (CLKOUT and REFOUT)
VDD OUTPUT 0V
Tr Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 3. Power Down Timing and Power Up Timing
POWER DOWN
VDD 0V VIL
VIH tPU
CLKOUT
(Asynchronous)
High Impedance
tSTP
Figure 4. Output Enable/Disable Timing
OUTPUT ENABLE VDD 0V VIL VIH
TOE2
CLKOUT
(Asynchronous)
High Impedance
TOE1
Document #: 001-15577 Rev. **
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PRELIMINARY
CY22180
Ordering Information
Part Number[6] CY22180FSXC CY22180FSXI CY22180SXC-xxx CY22180SXC-xxxT CY22180SXI-xxx CY22180SXI-xxxT CY3672-USB CY3619 Field Programmable, Pb-free Field Programmable, Pb-free Factory Programmed, Pb-free Factory Programmed, Tape and Reel - Pb-free Factory Programmed, Pb-free Factory Programmed, Tape and Reel - Pb-free FTG programmer CY22180FSXC and CY22180FSXI Socket adapter Description Product Flow Commercial, 0 to 70C Industrial, -40 to 85C Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C n/a n/a
Package Diagrams
Figure 5. 8-Lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Note 6. "xxx" denotes the assigned product dash number for devices that are factory-programmed.
Document #: 001-15577 Rev. **
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PRELIMINARY
Document History Page
Document Title: CY22180 Very Low Jitter Field and Factory Programmable Clock Generator Document Number: 001-15577 REV. ** ECN NO. 1058460 Issue Date See ECN Orig. of Change KVM/ New Data Sheet KKVTMP Description of Change
CY22180
Document #: 001-15577 Rev. **
Page 8 of 8
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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